Recently, progress has been made in the development of large capacity memory devices along with progress in manufacturing methods for semiconductor devices and increased applications in the field of memory devices. Especially by forming an individual memory cell having a single capacitor and a single transistor, considerable progress is being achieved in DRAM (Dynamic Random Access Memory) which is favorable to increase packing density.
In order to increase the packing density, the DRAM has been developed from a conventional planar-type capacitor cell structure to a three-dimensional structure, which is typically divided into two types, stack-type or trench-type, according to the memory cell structure.
In the trench-type capacitor, the widened inside walls of a trench formed by anisotropic-etching of a silicon substrate are utilized as a capacitor region, whereby sufficient capacitance can be available within a narrow region. This type of capacitor is more advantageous in planarization than that of a stack-type capacitor which will be described below. However, minor errors resulting from alpha particles and the leakage of current between the trenches by the scaling-down of the work make it difficult to form the conventional trench-type capacitor. On the other hand, the stack-type capacitor is manufactured by stacking a capacitor upon a silicon substrate, which makes it much less susceptible to minor errors due to a small diffusion region, and is relatively simple to manufacture. However, due to the structure of the capacitor stacked upon a transistor, the stack-type capacitor has a severe step coverage problem and has difficulties in growing a dielectric film.
When applying the above described three-dimensional capacitor cell structures to UVLSI memory devices below the order of a half-micron region, a stack-type capacitor or a combined stack-trench type capacitor having a large capacitor substrate topography has been proposed. The conventional manufacturing processes for the combined stack-trench type capacitor are illustrated in FIGS. 1A to 1E, and will be described below in detail.
FIG. 1A illustrates a process for forming a transistor and a trench 6 on a semiconductor substrate 100. At first, an active region is defined by depositing a field oxide layer 101 on the semiconductor substrate 100. A gate electrode 1, a source region 2 and a drain region 3 of a transistor which is an element of a memory cell are formed on the active region, and a first conductive layer 4, e.g., an impurity-doped first polycrystalline silicon layer, is formed on any predetermined portion of the field oxide layer 101 such that it is connected to a gate electrode of a memory cell disposed adjacently to the field oxide layer. An insulating layer 5, e.g., HTO (High Temperature Oxide) layer having a thickness of about 1500-1800 .ANG., is formed on the whole surface of the aforesaid structure. An opening is formed to expose a portion of the source region by applying a mask on the insulating layer formed on the source region, so that a trench 6 is formed by using the insulating layer in which the opening is formed.
FIG. 1B illustrates a process for forming a second conductive layer 7 serving as a first electrode of the capacitor, wherein the second conductive layer 7, e.g., an impurity-doped second polycrystalline silicon layer, is formed both on the inside of the trench 6 and on the insulating layer 5 by means of a low pressure chemical vapor deposition (LPCVD) device, to have a thickness of about 1000-2000 .ANG..
FIG. 1C illustrates a process for forming a photoresist pattern PR. As shown in FIG. 1C, the photoresist pattern PR is formed by conventional lithography such as by photoresist coating, mask exposure and development. During the process, the photoresist extends to the inside region of the trench 6, which is formed to be deep and narrow.
FIG. 1D illustrates a process for forming a first electrode pattern 7a of the capacitor, in which the pattern 7a is formed by etching the second conductive layer with the application of the photoresist pattern PR as a mask.
FIG. 1E illustrates a process for removing the photoresist pattern. After the process illustrated in FIG. 1E is performed, a dielectric film and a third conductive layer are formed on the first electrode pattern 7a in succession, thereby completing the manufacturing of the combined stack-trench capacitor.
In the conventional method for manufacturing the combined stack-trench type capacitor described above, after the second conductive layer serving as the first electrode of the capacitor is formed, the first electrode pattern is formed through photoetching. During the forming of the first electrode pattern, the deep and narrow inside region of the trench is covered with the photoresist of the photoresist pattern. Therefore, when removing the photoresist pattern after the first electrode pattern is formed by applying the photoresist pattern, the photoresist is not completely removed but adheres onto the second conductive layer formed on the inside walls of the trench, so that it is difficult to uniformly form a dielectric film. Further, when the capacitor is formed by depositing the third conductive layer on the non-uniform dielectric film, the reliability and electrical characteristics of the capacitor are negatively affected.